ATMEGA649V-8MI【PDF 127/146 页】IC AVR MCU FLASH 64K 1.8V 64QFN

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2552K–AVR–04/11

ATmega329/3290/649/6490

12.2

Register Description

12.2.1

EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 12-1. The value on the INT0 pin is sampled before detecting

edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt.

12.2.2

External Interrupt Mask Register – EIMSK

Bit 7 – PCIE3: Pin Change Interrupt Enable 3

When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 3 is enabled. Any change on any enabled PCINT30..24 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT3

Interrupt Vector. PCINT30..24 pins are enabled individually by the PCMSK3 Register.

This bit is reserved bit in ATmega329/649 and should always be written to zero.

Bit 6 – PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT2

Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.

This bit is reserved bit in ATmega329/649 and should always be written to zero.

Bit

765

4321

(0x69)

–

ISC01

ISC00

EICRA

Read/Write

RRRR

R/W

Initial Value

000

0000

Table 12-1.

Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

Bit

654

PCIE3

PCIE2

PCIE1

PCIE0

–

–INT0

EIMSK

Read/Write

R/W

Initial Value

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